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by Brian J Frohring Bruce E Peetz Mark A Unkrich and Steven C Bird

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IN THE PAST. fast, wideband waveform recorders have not kept pace with their lower-speed cousins in measurement fidelity. Therefore, the primary design objective of the HP 5185A Waveform Recorder was superior dynamic performance, requiring careful design of all subsystems affecting measurement performance. This article describes the key considerations involved in the design of the major analog components. We also discuss the most useful parameter for verifying dynamic performance, effective bits.

The essential elements of the analog-to-digital measurement system for one channel are shown in Fig. 1. The HP 5185A provides two identical digitizing channels driven by the common 2511-MHz SAW (surface-acoustic-wave) reference uscillator. Each channel includes several custom integrated circuits designed to provide the required measurement performance and feature set.

The 8-bit quantizer IC is the foundation of the measurement system. Minimizing on-chip delays and delay mismatches was a major consideration in designing this device for optimal dynamic performance. Matching requirements were satisfied through the choice nf converter architecture, cell design optimization, and chip layout. One of the performance characteristics resulting Irom this design effort is the absence of missing codes for full-scale input signals through 100 MHz. The relationship of on-chip matching to performance and the mechanisms that create harmonic distortion will be covered later in this article. Harmonic distortion resulting from the nonlinear nature of the quantizer input capacitance is also analyzed.

The attenuator, preamp hybrid, and op amp IC condition the analog input signal, providing continuously variable gain across all input ranges for optimum signal-to-noise performance. A selectable low-pass filter is useful to prevent aliasing ol the input signal and high-frequency noise while digitizing at the maximum rate. The general design requirements for these analog signal conditioning components are discussed and an analysis of low-order distortion in tlie differential input stage of the preamp IC is presented.

Phase noise in the sampling clock can degrade dynamic performance. We therefore describe the relation between various types and sources of phase noise and the effects of this noise on amplitude errors when sampling high-slew-rate signals. We then discuss considerations related to the choice of oscillator topology, circuit design, and compo nent selection to achieve the required performance in the SAW reference oscillator, that is, less than 2 ps rms phase jitter.

Finally, we review how dynamic performance is measured and outline the closed-form sine wave curve fitting algorithm used in production testing of the HP 5185A.

Analog-to-Digital Conversion

The analog-lo-digital conversion function is the most critical in the signal path of any waveform recorder. Realizing the dynamic performance objectives for the HP 5185A Waveform Recorder required careful minimization of the sources of error.

Many analog-to-digital converter architectures require the use of a separate sample-and-hnld circuit to sample the input waveform for subsequent conversion to a digital value. In the HP 5185A, both the analog sampling and the analog-lo-digital conversion functions are provided by a single monolithic integrated circuit, the quantizer This circuit performs a new conversion every 4 ns. ADC Hybrid. A custom bipolar operational amplifier IC functions as a fixed-gain atnplifer to drive the 25-pF capacitive load presented by the quantizer input. It converts the differential output of the preamp hybrid to a single-ended signal at the quantizer input, realizing a gain of ti.7 with a bandwidth greater than 220 MHz. The custom operational amplifier and quantizer are mounted in a thin-film hybrid package which is described in the article on page 49 Chip Architecture. The block diagram of the quantizer is shown in Fig, 2. This is the architecture of a classic flash ana!ng-tn-dlgital converter, having one comparator for each quantization threshold to be encoded. The buffer.'late lies, 256 for the 8-bit conversion, sample the analog input signal and output a "thermometer1' code representation of the

Fig. 1. Analag-ta-digital measurement system (one channel)

Analog In +Ret

Analog In +Ret

Ctock

Trigger

BI1s(4)

Fig. 2. 8-bit quantizer IC block diagram.

Ctock

Trigger

BI1s(4)

Fig. 2. 8-bit quantizer IC block diagram.

value of the input signal at the sampling instant. The decoding logic converts this ralher inefficient (25fi-bit) digital code to an 8-bit binary code. Although circuit efficiencies could be achieved by shifting some of the encoding function ahead of the sampling comparator stage,1 this more conventional approach equalizes the delay paths for all encoded states. Analog decoding before ihe first stage latches usually requires nonidentical cells with the resultant risk of adding code dependent delays to the input signal before sampling. To achieve a nearly square chip layout, the IC is divided into two 7-bit converter subsections.

The four extra comparators (the bottom ones in Fig. 2| represent a slight departure from the conventional flash architecture. These are identical to the sampling comparators and provide input signal threshold detection matched in time to the sampling process accomplished by the converter's main comparator bank. Two of these provide analog-digital trigger detection with hysteresis, and the other two are used for analog underflow and overflow detection.

Design Considerations

The key design considerations for maximizing the dynamic performance of the quantizer were;

• Layout of the input comparators and associated interconnect for optimum delay and load matching

• Selection of an error-tolerant encoding scheme providing matched loading on the input comparators ■ Comparator design lo minimize the sampling latch regeneral ion time constant, thus minimizing the probability of internal ambiguous logic levels which may result in output bit errors. Variable Comparator Delay, When a flash analog-to-digital converter is integrated, the propagation delay of two identical gates on the sume circuit may differ. If the propagation delay variance among comparators is large, errors can occur when the analog input is sampled. The signal corruption becomes significant when the delay difference belween two comparators becomes so great that, for high-slew-rate signals, two consecutive comparators switch in the wrong order, resulting in an invalid state of the thermometer code at the output of the sampling comparators. For a full-scale 125-MHz sinusoidal input converted to 8 bits, this mismatch amounts to about It) ps.

To reduce the variability of the comparator delays, Ihe buffer and latch transistors in the signal path are biased al currents below that of the fT peak. At low collector currents, fT is dependent on transit time, thermal voltage, and collector current (Fig. while at higher collector currents, the Kirk effect" limits fT. Biasing the transistors at the fT peak would make fT, and hence the delay, dependent on both transit time and Kirk effect. Although the reduced bias approach makes the average propagation delay greater, il reduces Ihe comparator delay variance by eliminating the device matching requirements for the Kirk effect. Encoding. To reduce further ihe effect of comparator delay mismatch, a compact encoding scheme was chosen that produces the most benign results for likely Invalid stales. Based on simulations of several techniques for binary and nonbiliary encoding, the optimal approach produces an 8-bit binary code at the quantizer output.

As mentioned previously, the 3-bit converter is divided into two 7-bit subsections. The first-level encoding for each subsection converts the 128-bit thermometer code generated by the bank of comparators into a 32-bit intermediate code.

The first-level encoding scheme significantly reduces metal interconnect by allowing the comparator cells to be

Region ot Dominance by Transit Time tf

Fig. 3. Transistor f, as a function of collector currer,

Fig. 3. Transistor f, as a function of collector currer,

Signal Ret

Fig. 4, Comparators are interleaved by four in the quantizer IC input network.

Fig. 4, Comparators are interleaved by four in the quantizer IC input network.

adjacent to the first-level logic cells, thus saving die area. In addition, the scheme maintains equal loading on the comparators to avoid mismatched propagation delay. The encoding for a 7-bit subsection is given by the following Hoolean logic relation:

where H(n] is the nth bit of the partially encoded word. CJx] is the output of the xth comparator, and n ranges from 1 through 32. This scheme allows comparators to be interleaved by four on the chip layout as shown in Fig, 4. yielding a benefit of longer metal runs on the resistor ladder to improve matching of the one-ohm-per-tap values. For the final conversion, the encoding algorithm that proved most tolerant to invalid states was implemented. Regeneration Time Constant. For any binary encoding technique, two or more output bits may change for a single input threshold transition. If the input signal level is close to the first-stage sampling latch balance point at such a threshold transition, the comparator output may not have regenerated to a valid logic level when the output latch stage is latched. If the encoding logic for any two of the affected output bits interprets this level differently, an erroneous output code can result. Civen a uniformly distributed input, the likelihood P of an error can be derived:'

where V, is the ambiguous voltage range of the comparator output logic level, A is the analog gain of the comparator, q is the voltage span between two adjacent input comparator thresholds, T is the time available to latch, which is constrained by the time between the input comparator and output latch docks, and t is the comparator positive feedback (regeneration) time constant.

Since a binary scheme was chosen to minimize the variable comparator delay problem, the comparator (Fig. 5) is designed to minimize P in equation 1 above. In a typical latch. R5 and R6 are effectively zero-valued and only R3 and R4 can be varied. In such a configuration, larger values of R3 and R4 increase the positive feedback loop gain but have the undesirable effect of increasing latch recovery time, the time required for the comparator to go from a latched state to tracking the input writh no memory of its previous state. Splitting the latch load resistors is key to achieving an optimal trade-off among latch gain, regeneration time constant t. and latch recovery time. The sum of resistors R3 and R5 (identical to R4 and Re, respectively) is made large to increase the positive feedback loop gain, thus decreasing -. An independent choice of R3 optimizes latch recovery time. For a fixed sampling period, reducing the latch recovery time increases the time available to latch, T.

Systematic Comparator Delay Mismatch, On a chip large enough to house 256 comparators, the mismatch in the propagation of the input and latch signals can generate significant amounts of error. These signals are routed on separate lumped RC lines. Because of the RC characteristic and the short length of the line, no attempt was made to terminate the line in its characteristic impedance. Model-

Analog Iripul

Fig. 5. Quantizer IC comparator celt schematic.

ing the lumped open-circuit line as a distributed system, the velocity of propagation for a line that is short compared to the wavelength of the applied frequency is:"*

y y where s is complex frequency, y is line position (y = 0 at the end of the line), and y is the line characteristic. The line characteristic is dominated by distributed metal resistance, distributed metal capacitance, and lumped transistor capacitance. Inductance is negligible in the frequency range of interest on IC metal traces for the purposes of propagation delay. Distributing the transistor capacitance, the line characteristic is given by:

Substituting equation 3 into equation 2 gives the velocity:

frequency testing? can be used to measure this effect.* The plot in Fig, 6 shows such a test under the most severe conditions—sampling at the maximum rate with an input frequency near half the sampling rate. The data has been decimated by plotting every other point to realize an effective sampling rate of 125 MHz. As expected, the nonlinear delay shows up as parabolic distortion, which can just be perceived riding on the rising edge of the sine wave, This amounts to mismatch on the order of 10 ps over the entire line. Analytically, this kind of nonlinearity can be treated as frequency modulation by Bessel functions,6 giving energy in the 21st, 23rd, and 25th harmonics for a full-scale input.

Distortion Sources. As can he seen in Fig. 7, both second and third harmonic distortion increase at high input frequencies, Second-order distortion HD, is a result of the nonlinear base-collector capacitance Cjr of Q1 in the input latch (Fig. 5) and the finite source resistance driving C„. This source resistance results from the op amp output impedance and series resistance in the op amp/quantizer interconnect network. Analysis using Volterra series gives the result:

By integrating I he inverse of equation 4 from some point y, on the line to the end of the line, the propagation delay is found:

delay =

RCyi

Optimal matching of RC hetween the input line and the latch line is achieved by running both lines on the same layer of metal and matching the transistors connected to the line. Monideal matching would be seen as eight parabolic lumps over the input range of the converter. The number eight arises from the interleaving of comparators by four (Fig, 4) in each of the two 7-bit subsections. Beat

- Full Scale

Fig. 6. Beat frequency plot for a signal at 125 MHz - 1 00 Hz sampled at 250 MHz.

VowCnR

where V„ is the magnitude of the fundamental, tu is the input frequency, CL, is the linear voltage coefficient, that is, the coefficient of the V1 term in a power series expansion of Cjc[V). Cfo is the constant term in the power series expansion of C|C(V), and R is the source resistance. Since the source is inductive as well as resistive, R could be replaced with a more complex expression that takes the inductance of the source into account.

Third-order distortion arises from multiple sources. In addition to the nonlinear RC mechanism just discussed, the latching of high-slew-rate signals by finite-rise-time latch signals can generate third-order distortion. This latter effect can be understood by referring to the simple latch

'Beat frequency lesting :s a (oc^nque of undersampipg a high-frequency input s.ne wave at a rati? sbghrfy olfse! from ¡he input frequency The input frequency b mi.yea lo a tower frequency where tl can be viewed n deta

o" cd

Effective Bits

Third Harmonic Second Harmonic

Effective Bits

Frequency (MHz]

1000

Fig. 7. Distortion ana effective bits versus frequency for the anatog-to-digital converter of the HP 5185A Waveform Recorder.

of Fig. 8. if the latch command is in the track mode, all of the current passes through the lefthand differential pair and the output follows the input. As Ihe latch command state is slowly changed, some current starts to flow in the righthand pair. The input-output transfer function starts exhibiting hysteresis because of the positive feedback of the righthand pair. As more current is switched, the amount of hysteresis increases until the circuit is fully latched. If the latch command is switched at full speed, the circuit still passes through the period of increasing hysteresis, although quickly.

A quasistatic analysis of the two upper pairs in Fig. 8 results in the hysteresis boundary:

where V, is the hysteresis boundary as viewed from the input, V, is the thermal voltage. I, is the total comparator stage current, i, is the sum of the emitter currents in the righthand pair, I2 is the sum of the emitter currents in the lefthand pair, and Yi is the logic level. I,RL. Assuming that the currents 1, and I2 switch uniformly with time, equation 5 is plotted as a function of time in Fig. 9. Also plotted in Fig. 9 are lines representing two signals, one quickly varying, the other slowly. As long as a signal stays within the area labeled "latched region" after initially entering this area, the signal will be latched correctly. But if a signal enters the latched region and then leaves it before being latched, it will be latched incorrectly.

To see how errors arise, first consider a slow-moving signal. Since it enters the hysteresis boundary from below and later is latched low, we can think of the sample instant as occurring near the onset of the hysteresis, before point A in Fig. 9. Now consider the fast-moving signal. It also enters the hysteresis boundary from below but passes above the hysteresis boundary before being latched, resulting in a high value. In this case, the sampling instant is effectively after point B in Fig. 9. later than for the slow-moving signal. Since this speed dependent delay occurs equally for both rising and falling inputs, it results in odd-harmonic distortion.

Input i Voltage

Hysteresis -Boundary

				Output ^
:	1
1	u	VJ

Fig. 8. Simple latch.

Hysteresis -Boundary

Input i Voltage

Hysteresis Boundary

Fig. 9. Hysteresis boundary versus time for the larch of Fig 8

Hysteresis Boundary

Fig. 9. Hysteresis boundary versus time for the larch of Fig 8

Assuming that signals are constant-slew ramps over the input range near the comparator threshold, and that tail currents switch uniformly with time, the projected error boundary based on equation 5 is :

dVj_ dt

Fig. 8. Simple latch.

where Vf is given by equation 5. t, is the time that describes the states of currents I, and l2 when a constant-slew signal is tangent to the hysteresis boundary, and t^ is the time that describes the stales of currents 1, and l2 at the onset of hysteresis.

This hysteresis-based source of distortion can be reduced by using lower values of R1 through R4 (Fig. 5), which reduces the slew rate seen by the sampling latch circuitry. The split load scheme of the latch portion is particularly helpful in keeping R3 and R4 low.

Distortion in the Signal Conditioning Path

Having taken great care to realize unsurpassed dynamic performance in the 8-bit quantizer, we could not allow the analog signal conditioning path to compromise this performance, Components in the analog chain are therefore designed with aggressive goals for low distortion, low noise, and wide bandwidth. The input stage of the preamp provides a useful vehicle for discussion of several design issues related to distortion.

A high signal-to-noise ratio is desirable to minimize the rms noise during a measurement. Increasing the signal levels to maximize the signal-to-noise ratio must be balanced with the errors introduced by the resulting increased levels of distortion. Second-order harmonic distortion is proportional to the input signal level and third-order distortion is proportional to the square of the input signal level.

Mreamp Hybrid. The preamp [Fig. 10) is based on a pair of custom bipolar integrated circuits produced in HP's 5-CHz-fT high-frequency bipolar process. The input cascode transconductance of the amplifier is selectable for three values in a 1-2-4 sequence by effectively switching the

Clamp Circuit

where

Assuming a sine wave input, Iv = AsinM), no offset, and low distortion levels such that second and third-order harmonic distort ion are dominated by the second and third-order non linearities, respectively, the distort ion lermsare:

Current Amptttim

	'OACt --fv	Vamlar QAC Control
Foil r-Quad rarrl Multiplier	w

Cascode Transconductance Input

Fig. 10. Simplified input preamplifier schematic diagram.

Cascode Transconductance Input

Fig. 10. Simplified input preamplifier schematic diagram.

value of the emitter degeneration resistance R. With one of the inputs incrementally grounded, the single-ended-to-differential conversion is performed. Examining distortion from this stage, the simplified transfer function for the emitter degenerated differential pair of transistors Q1 and Q2 can be derived from:

Av = 2V,tanh"1 ("¿j ) + RAi where Av is the differential base voltage VbQ1 - Vhq,, Vt is the thermal voltage, Ai is the differential collector current 'cqi — ^cQ^t R is the emitter degeneration resistance, and I is the emitter and collector bias current ignoring ,8 effects. Using a Taylor series expansion and collecting the terms,

Inverting this equation gives the transfer function: I VtI

V, + RI *** 12(V, + RI)4 The output differential current is of the form

For the maximally stressed gain range and operating conditions of I = 8 mA, R - 170 . V, = 26 mV at 25°C, and maximum input level A - 50 mV, the dominant distortion term is HD3 = -71) dl3, In practice, HD^ is generated by internal mismatches and offsets in the input signal resulting in distortion terms up to the level of HD;i, but these have been ignored in the analysis.

SAW Oscillator

An important source of error in any high-speed analog-to-digital converter is ihe phase noise, or cycle-to-cycle jitter, of the oscillator that provides the master sampling clock. Time jiller of the clock alters the time between successive samples in a random fashion. This time jitter can be directly related to amplitude errors at the oulput of the ADC. If ihe jitter of the oscillator is too high, it contributes to sampling errors [amplitude noise) for points sampled on ihe high-slew-rate portions of input signals. As a practical design goal, the jitter of the oscillalor should be low enough to produce no more than Vaq of amplitude error under the worst-case conditions, where q is the average voltage span between adjacent comparator thresholds.

The worst-case phase noise requirements for the master reference oscillator of the HP 5185A are strict. Assuming that the Nyquist sampling theorem is not being violated, the worst-case conditions are; • Sampling at sine w:ave zero crossings

■ Maximum sample rate of 250 megasamples per second

■ Input frequency of 125 MHz

■ Full-scale signal at the input

■ Maximum memory record length of 64K words. Under these conditions the jitter requirement corresponding to amplitude noise of no more than Vi LSB is 2 ps rms, which is computed from the following equation:

200 ps 20 ps 2 ps

Fl i cher-ci-Frequency Process f, = 2.5 MHz

White Phase Noise Floor

Fl i cher-ci-Frequency Process

(Worst Case]

(Worst Case]

Fig. 11. Time-domain phase ncse requirement for the HP

5185A.

where fm is the input frequency, N is the number of bits, and 2.5 is taken to be a peak-to-rms conversion for a Gaussian distribution. This jitter requirement must be held for the duration of a worst-case measurement, which is four nanoseconds per sample limes 64K samples per measurement. or approximately one quarter of a millisecond. The white phase noise floor, shown in Fig. 11, defines the jitter performance requirement under worst-case conditions. This plot shows rms jitter o\<(t) versus time t, where t is the total measurement duration. Note that the worst-case requirement is relaxed for lower input frequencies and sample rates.

The time-domain plot of Fig, 11 can be transformed inlo a frequency-domain plot of the phase noise requirements.a Fig, 12 is such a plot showing the SSB phase noise spectral power density (in dBc/Hz) as a function of offset from the carrier (in Hz), Fig. 12 shows that the 2-ps noise floor requirement derived in the time domain transforms into a noise floor of 148 dB/Hz below the carrier in the frequency domain.

The requirements can be directly compared with the measured phase noise performance of the HP 5185A oscillator. also shown in Fig. 12. The overall system performance is dependent upon the integral of the phase noise margin over the full bandwidth of the system. The cumulative margin is large compared to the cumulative loss of the corner violation shown, so the corner violation has little effect on the overall system performance. (The narrowband spikes in the 10Q-kHz-to-40-MHz range are artifacts of the measurement system.)

SAW Oscillator Phase-Locked Loop. Fig. 13 shows a block diagram of the surface-acoustic-wave (SAW) phase-locked loop (PLL). The heart of this circuit is the voltage-controlled oscillator (VCO). The SAW VCO provides the sampling clock to the ADC in each channel.

The major components of the VCO circuit use custom technology. The crystal is a SAW device developed for this product at Hewlett-Packard's Santa Rosa Technology Center." The SAW device was selected because of its excellent phase noise characteristics. It is a fundamental-mode device, which can be modeled as an LG series-resonant circuit, allowing a simpler design than must RF oscillators.

The active device chosen for the SAW VCO is a differential amplifier made from custom emitter-coupled logic fabricated at the Santa Clara Technology Center. This differential amplifier was selected for its low phase noise floor and because it can deliver fast edge speeds (t20 ao = 350 ps]. Maintaining fast edge speeds throughout the sampling clock chain minimizes the phase noise contribution of each stage in the chain. To preserve the quality of the YCO output, the encode multiplexer, synchronizer, and output drivers are also implemented in custom emitter-coupled logic.

The phase-locked loop operates in the same fashion as most conventional phase-locked loops. Phase-locking allows the VCO to take on the superior aging and temperature stability of the reference (internal or external] while retaining its own short-term stability'. Phase-locking to an external reference also allows the user to stabilize the phase relationship between the sample clock and the input waveform, provided that the input waveform is coherent with the reference.

Design Considerations. The noise process that dominates the SAW phase-locked loop jitter performance is the white phase noise process. This process is a result of the noise floor of the differential amplifier used in the SAW VCO, Buffer stages between the VCO and the ADC sampling clock input also degrade the noise floor of the sample clock. This degradation can be calculated using a root-sum-squares formula. For example, adding a second stage with a noise floor identical to the VCO noise floor will degrade the noise floor of the sample clock by 3 dB. A third stage will degrade the noise floor by an additional 1.77 dB, and so on. Therefore, minimizing the number of buffer stages is important.

The differential amplifier, like all amplifiers, has 1/f noise around dc and has some inherent nonlinearities. In an oscillator, these nonlinearities mix the 1/f noise onto the carrier. The SAW resonator, modeled as a second-order bandpass filter, produces a 1/f2 process. Mixing 1/f with 1/f2 produces the 1/f3 phase noise process shown in Fig. 12. Consideration must be given to both the amplifier linearity and the Q of the crystal since together they determine the corner frequency between the white phase noise floor process and the 1/f"' process. This corner frequency becomes more important for longer measurement durations.

Phase Noise Requirements for the HP 5185A

Phase Detector -120 4- Noise Floor

Measured Performance of the SAW System

IK tOK

100K tM

Phase Detector -120 4- Noise Floor

Measured Performance of the SAW System

IK tOK

100K tM

Fig. 12. Frequency-domain phase noise requirement and actual performance

There is another noise floor closer to the carrier—the noise floor of the phase detector. This noise floor and the i/t3 process meet at an offset from the carrier of approximately 100 Hz. This offset provides the optima) bandwidth for the low-pass filter that follows the phase detector. If the bandwidth is too wide, the 1/f3 performance of the SAW resonator will he degraded. If it is too narrow, the phase detector performance will he degraded.

The pulling range of a VCO is the amount by which the VCO frequency can be shifted from the nominal frequency by varying the input control voltage. The pulling range must be large enough Lo compensate for the aging rate of the SAW resonator, the temperature dependence of the SAW device's parameters, and center frequency tolerances in the SAW manufacturing process. However, when the pulling range is increased, it is at the expense of the overall Q of the circuit. This increases the phase noise in the 1/f region and pushes the corner frequency outward. The pulling range of the SAW oscillator is maximized through the use of back-to-back, low-capacitance varactor diodes in series with the SAW resonator in the oscillator feedback loop.

Making Effective Bits Measurements

Effective bits is a figure of merit used to quantify the contributions of all forms of distortion and noise added by the measurement process: quantization error (differential nonlinearities, missing codes, and aperture uncertainty], integral nonlinearlty (harmonic distortion), and system noise (additive noise and spurious nonharrnonic spectral components). The method of measuring effective bits described in previous publications3'1" and now generally (but not universally) used for specifying the performance of digitizing instruments uses sine wave curve fitting. The test technique involves making a measurement of a single-frequency sinusoidal input, estimating the actual input by fitting a sine wave to the data using a least-mean-squared-

error algorithm, then calculating the residual rms error in the measured data relative to the fit sinusoid. Effective bits is then defined as follows:

Effective bits = N — log where N is the number of bits of resolution of the digitizer being tested, Ea,.luai is the residual rms error in the measured data after subtracting the fit sine wave, and EMcal is the expected value of the rms error an ideal N-bit quantizer adds to a uniformly distributed input signal, q/V12, where q is the voltage span between adjacent comparator thresholds.

Since the effective bits parameter is sensitive to all forms of distortion and noise, it is important that care be taken to ensure that the test system used to evaluate the performance of an instrument under test makes no significant contribution to the detected rms error.

The basic test setup required to measure the effective bits performance of a given instrument is shown in Tig. 14. The bandpass filter is present to reduce harmonic distortion components from the generator output to a negligible level and to ensure that no signal-gene rat or-produced or coupled low-frequency noise is present at the input to the instrument under test. The major sources of potential errors in the measurement of effective bits are signal generator phase noise and amplitude errors (inaccuracy of the signal generator output, losses in the bandpass filter, and cable losses).

Signal generator phase noise represents a deviation from the ideal sine wave assumed to be present at the input. The nearly uniform sampling of the instrument under test translates signal generator phase noise into amplitude errors, which are most pronounced near zero crossings. These errors are readily detected in effective hits measurements.

External Reference (1.2. 5,10 MHz)

External Encode (DC to 250 MHz)

TII-MHi Inlemal Oscillator

ADC 1 Sample Clock

External Reference (1.2. 5,10 MHz)

External Encode (DC to 250 MHz)

Out ol Lock

Buffer

TII-MHi Inlemal Oscillator

ADC 1 Sample Clock

Out ol Lock

Buffer

Fig, 13. 350-MHz S/W oscillator phase-locked loop system.

Frequency Reference Locking Connection

Rg. 14. Effective bits test setup

An HP 8662A Synthesized Signal Generator is used in all HP 5185 A test systems at the factory because of its excellent phase noise characteristics.

Since the effective bits parameter measures distortion as well as noise, testing will be sensitive to variations in the input amplitude when measurement distortion is not negligible. This generally occurs at higher input frequencies. The absolute accuracy of the synthesized signal generator, specified at ±1 dB. plus attenuation of the fundamental bv the bandpass filter, require amplitude compensation of the generator output to provide the proper amplitude at the input of the instrument under test. In production testing, these losses are corrected by identifying the amplitude settings that result in the proper signal amplitude at the instrument under test. This is accomplished through an automated calibration procedure using an HP 438A Power Meter with HP 8482A Power Sensors. Amplitude errors of a few dB are reduced to well under ±0.5 dB through this calibration process.

Acknowledgments

The authors are greatly indebted to the following people who contributed to the performance of the HP 5185A Waveform Recorder. The input attenuator module was designed by fim Johnson. Jeremy Sommer took time away from his switching power supply design to improve the dynamic performance of the integrated blocks. The opera tional amplifier in the ADC hybrid was designed by James Kang, who also contributed to the design of the quantizer. Most of the quantizer circuitry wras designed by Brian Hamilton. John Schmitz refined the critical oscilla tor-to-quantizer timing. The assistance and technology of the Santa Clara Technology Center are greativ appreciated. The fixed-frequency sine wave curve fit method was derived by Ron Potter.

References

1. ]. Corcoran, k. Kmidsen. P. Clark, and D. Hiiler. "A 400 MHz 6b ADC." IS SCC Digest of Ter fini™ J Papers, TEEE Cat. Nu. S4CH1971-1. February 1984. pp. 294-295.

2. C.T. Kirk, Jr.. "A Theory of Transistor Cutoff Frequency lir] Fallout at High Current Densities." IRE Transactions on Electron Devices, Vol. ED-9, 1962, p. 164.

3. B. Zojer. R. Peschacher, and W. L use h nig. "A 6 bit 200 MHz Full Nyquist A D Converter." IEEE Journal of Solid-State Circuits. Vol. SC-20. no. 3. June 1985, pp. 780-786,

4. B. Peetz. 8. D. Hamilton, and J. Kang. "An 0-bit 250 Megasample per Second Anaiog-to-Digital Converter: Operation Without a.Sample and Hold," JEEE Journal of Solid-State Circuits. Vol. SC-21. no. S, December 198fi.

5. Dynamic Performance Testing of A-to-D Converters, Hewlett-Packard Product Note 518nA-2. 1982.

6. M. Schwartz. Information Transmission, Modulation, and Noise. McGraw-Hill, 1959, Chapter 3.

7. S.C. Bird and J.A. Folchi, "Time Base Requirements for a Waveform Recorder," Hetvie It-Packard Journal. Vol. 33, no, 11. November 1982, gp, 39-34.

8. M.C. Fischer, "Frequency Stability Measurement Procedures." Eighth Annual Precise Time interval Applications and Planning Meeting, December 1976.

9. P.S. Cross and S.S. Elliot. "Surface-Acoustic-Wave Resonators." Heivlett-PockorrJ Journal, Vol, 32. no. 12, December 1981, 111. 6.E. Peetz, A..S. Muto, and ].M. Neil, "Measuring Waveform Recorder Performance," Hewlett-Packard Journal. Vol. 33, 110. 11. November 1982.

Fixed-Frequency Sine Wave Curve Fit

Estimation of the rms error contributed by the quantization process is the purpose of sine wave curve fitting A sinusoid fit to the input data using a ieast-mean-squares algorithm is assumed to represent the actual input signal presented to the digitizer being tested As discussed in the accompanying anicle the effective bits parameter is based on the rms noise power present in the error signal—the difference between the digitized data and the fit sinusoid—over the period of the measurement record.

Any fitting algorithm fits a sine wave of the following form-V,„(nJ = VD + Va cos (2irfinnTEamDlffl + <t>)

A generalized fitting algorithm requires fitting the parameters V0, Va, fjn, and $ in the above equation. Such fitting algorithms are iterative and therefore time-consuming and prone to undesirable convergence behavior because of the nonlinear relaiion between parameters.

Connecting the ext ref input of the instrument under test to the signal generator reference output phase-locks the sampling process to the input signal. The frequency of the input sinusoid is thus known to sufficient accuracy to enable use of a simplified sinusoidal curve lilting algorithm.

To derive the simplified algorithm, fit a sinusoid of the following form to the Input data xn = Ac os (tut „) + Bsm(utri) + C

where to is 2irflrl. f,n being the known input frequency, and the tn are the sample times

Given a data record yn of M samples of the input sinusoid measured at limes tn (in practice, uniformly separated by the sampling interval, T5amDle). the total residual error e of Ihe measured data relative to the fit sine wave Is given by:

* = S (yk-xk)2 = s y,-Acos;u,tk)- ßsin(«:j c]B k=1 k = :

Setting the partial derivatives with respect to the parameters being fit to zero gives:

0= -¿t- = -2 X [ y k ~ A cos(d)tk ) - B S in ( u>tk) - C ] COS{ u>tk ) oA k = !

M MM

The fit parameters are thus given by the solution lo the linear equation which is where:

2 yk"k

1 YkAi

The total residual error is given by:

Defining ct„ = cos (tilk) and ft = sin (utk) gives e = s0 - 2AY, - 2BY2 - 2CY3 + A2Un + 2 ABU ,2 + 2ACU13 + B2U„ + 2BCIU + MC3

and ihe rms error is then

2 yk«* = A 2 + b 2 akßv + c 2 ak k= 1 k=1 k=1 k=1

Using this fixed-frequency curve fit has reduced test computation time by a significant factor over the previously used variable-frequency curve fit.10 Fixed-frequency sine wave curve fitting Is a closed-form noniterative solution ensuring convergence The fixed-frequency curve fit thus provides a faster, more reliable measure of effective bits performance.

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